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C n , then Equation 1. The output buffer current drive capability may be 2mA, 4mA, etc. The output buffer may be designed to limit the signal slew rate The output buffer may be omitted input pad The pad may have a pull-up resistor or pull-down resistor The input receiver detect level may be TTL 1. Power and ground pads provide connections to the various ASIC power and ground busses. The metal connections from the pad to the power or ground bus within the power and ground pad or to the ASIC core are made as wide as possible and on as many metal layers as practical to minimize their resistance and maximize the current carrying capacity.

Because no other circuitry is required, the area in power and ground pads is often used for special ESD clamping circuitry that is associated only with power busses and not with any particular signal pin. The pre-driver defines the pad functionality and the driver is simply a large inverter connected to the PAD. Highspeed pre-drivers can cause sharp current spikes during operation. These current spikes can inject noise into the power supply especially when a large number of input and output signals are switching simultaneously.

This may require a slowing down of the pre-driver by means of slew rate control. This can be prevented by adjusting the timing of the transistor gate terminals to make sure each transistor is off before the other transistor turns on. Because the supplies connected to the driver transistors are subject to large current spikes and the resulting noise, it is common to isolate these supplies from all the other supplies on the ASIC core.

Typically, the pre-driver is designed to meet both the slowest and fastest ASIC design conditions. In the slow case, if the pre-driver is too slow, then there will be unwanted data dependency jittering. This data dependency jittering occurs when the pre-driver output voltage does not reach the full power supply voltage level within the data cycle time. On the other hand, in the fast condition, the pre-driver has high current consumption and sharp transients, which lead to simultaneous switching noise. Thus, it is imperative that these two conditions, or constraints, i.

Large currents occur during output transitions when external capacitances are rapidly charged and discharged. Large currents also occur when there is signal overshoot and a clamping diode becomes forward biased. In addition, large currents occur when a high voltage is rapidly discharged through the ESD protection devices. In addition, precise methods of inserting resistance between the PAD and transistor drains as well as general guidelines for placing body ties and latch-up guard rings are used.

Similar to the current path verification, it should be noted that some rules and guidelines such as electrical rules cannot be checked by means of physical verification. Therefore, careful simulation and proper layout style are necessary e. In practice, the pad pitch and the pad opening size is set by the mechanical limitation of packaging tools and the probe diameter of test equipment used to test an ASIC at wafer level. For an ASIC that is pad-limited, the pad pitch should be as small as possible to reduce the die size.

Chapter One 22 The two primary clamping diodes D1 and D2 will turn on if the PAD voltage rises above the power level or drops below the ground level. This allows the clamping devices to have time to turn on and prevent damage to the gates of M3 and M4. This resistor and associated RC delay create design challenges when dealing with high-speed input pads. In this case, the drain, body, and source of the transistors form a bipolar transistor known as a snapback device.

When the voltage and current of the snapback device reaches a trigger voltage and current, the voltage will snap to a lower level and the resistance of the device becomes very low. This condition can easily damage the transistor when the snapback is localized to only one portion of the entire channel region, otherwise known as a hot spot. For this reason, the resistance from the pad to all portions of the channel region must be as uniform as possible to ensure that the entire channel enters the snapback Libraries 23 mode simultaneously.

The transistor layouts use multiple fingers with with identical metal widths, contact-to-gate spacing, etc. These clamping devices may be simple diodes when connecting two supplies having the same voltage — such as digital ground to an isolated analog ground. For clamps between power and ground, as shown in Figure , a single transistor may be used as a snapback device or it may be used for more complex circuits such as diode stacks for low voltage supplies or large transistors with transient detector circuits.

This is because signal overshoot causes the transistor drain-body diode to become forward biased, resulting in current flow through the substrate. The latch-up phenomenon is well understood and is inherent to bulk CMOS processes. The result of this effect is the shorting between power and ground lines that can lead to ASIC self-destruction and system power failure. The output driver transistors that are directly connected to the PAD are each isolated within their own rings.

Most of the time, these timing models are generated by means of automation. Software for this purpose is usually available from EDA companies that are specialized in library characterization. Characterization tools take user-defined input waveforms and perform various transistor-level circuit simulations under several conditions to generate circuit responses for each element in the library.

The generated circuit responses will undergo some data processing to produce timing models for importing to logic synthesis, place-and-route, and logic simulation tools. During timing model generation, two main components are the subject of interest — propagation and transition delay. These are: x Linear or scalar delay model x Nonlinear delay model Chapter One 26 x Polynomial delay model x Current source delay model In the linear or scalar model, the total cell delay is a function only of load capacitance as shown in Figure The f 0 a parameter is a representation of total cell delay with zero loads.

The slope of the line b is considered as the cell drive strength and the product term bx can be viewed as rise time t r or fall time t f. In a nonlinear delay model, the effect of the input transition of the waveform is included in the cell delay calculation. There are two methods used to express this type of delay model — cell delay and propagation delay. In the cell delay method, the values of t pLH , t pHL , t r and t f are specified separately. In this method, the values of t pLH and t pHL represent the entire delay of standard cell from input to output without addition of the values of t r and t f.

In the propagation delay method, the total cell delay is specified as the sum of t pLH , t pHL , t r and t f. Therefore, the values of t pLH and t pHL are calculated based on the delay of cell from input until the beginning of the output transition. The coefficients a , b, c, and d can be determined by the fact that the propagation delay must cover the four delay corners as shown in Figure It is interesting to note that in discussion of such a model, if the input transition delay is large compared to the total cell delay, then the propagation delay becomes negative.

This negative time evaluation might occur when the output changes before the input reaches the logic switching threshold voltage. Although this negative value is alarming, it is not a problem as long as the cell delay is a positive value. Therefore a careful model validation is required when using this type of models. To generate a timing model for a given standard cell using a nonlinear model, circuit simulations are performed to measure the propagation delay for various input transitions and output capacitance loads.

For example, for six different input transitions and six output capacitance loads, there are thirty-six circuit simulations. These generated numbers are then stored for use by the static timing analysis tool. The timing analysis tool uses interpolation to calculate the delay number inside the table and extrapolation for the numbers that are located outside the table.

This concept is shown in Figure Figure Nonlinear Delay Table Libraries 29 The number of rows and columns that correspond to the input transitions and output capacitance loads play an important part during static timing analysis. The larger the table, the more characterization time will be required. The input transitions and output capacitances used in the table need to be selected to cover most of the real situations to avoid timing analysis engine extrapolation beyond the table.

Extrapolation beyond the table range may lead to inaccurate results. The extrapolation beyond the table range is the fundamental problem with this model as it relies too much on the local information e. The model is not suitable for extrapolation when it is necessary to evaluate the propagation delay outside the area defined by entry points in the table. It is important to note that the importance of the nonlinear term xy diminishes as the number of entry points or grid size increases. Therefore, the nonlinear Equation 1.

For example, for a seven input transition by seven output capacitance table there are forty-nine circuit simulations required to compute propagation delay for various conditions of temperature, process and voltage e. Owing to the wide range of process and supply voltage variations and the static nature of linear and nonlinear delay models, these models are no Chapter One 30 longer adequate to model the delay for deep submicron processes. To address this issue, the polynomial delay model has been suggested. Mathematically, two factors complicate the principal computation of such a model.

One is the order of the equation i. The values of l , m , n , and o are in order of twenty or more, depending upon desired accuracy. To compute the values of the K abcde coefficient, least-square error-curvefitting can be used. This means that one must determine the values of the K abcde coefficient such that the difference between the measured value f i and the calculated value f xi , y i , wi , z i at the sample point of i are minimized.

Since the values of the K abcde coefficient are chosen so that the function G assumes its minimal value, if the errors follow a normal probability Libraries 31 distribution, then the minimization of G produces a best estimate of the K abcde coefficient [5]. Similar to the polynomial delay model, Current Source Modeling CSM is another new equation-based approach to predict the cell timing delay. There are two main advantages of using the CSM delay modeling technique. One advantage is that the CSM is much simpler in comparison to the polynomial delay modeling and provides the same level of accuracy.

The difficulty with polynomial delay modeling is fitting the actual nonlinear nanometer effects in silicon using a polynomial equation with a limited number of variables and coefficients. CSM, on the other hand, is based on the topology and actual construction of the transitors and, thereby, accurately models the silicon nanometer effects by tracking nonlinear transistor switching behavior.

Another advantage is that the CSM models the output drive of a cell as a current source rather than a voltage source. Thus the delay and transition time can be derived from the mean current delivered by the gate into the load. Therefore, using mean current has a tendency to simplify the complex computation of effective capacitance loading by describing the effects of resistive shielding. It is key to note that in comparison of each of these delay models linear, nonlinear, polynomial, and current source , the underlying CMOS theory remains the same and the only change is the approximation used.

Apart from process and temperature variations, these models or functions represent the impact of resistance and capacitance on timing. With future ASICs, where the inductance of lines will play an important role, these models will need to be refined so that they can present the cell delay timing more accurately. Regardless of which model one may choose, a series of circuit simulations need to be performed for various conditions in order to generate the proper models for timing analysis.

The most standard simulation conditions are as follows: x Temperature range x Voltage range Chapter One 32 x Process corners x Threshold voltages There are four classes of operational temperature ranges as shown in Figure Room temperature 25C is considered typical, or normal, for the temperature range condition. Figure Operational Temperature Ranges However, during physical design it is prudent to use a standard cell library that is characterized for the lower and upper temperature ranges.

In generating simulations for process corners, one should note that the CMOS process has two steps — transistor formation, and metallization. Usually, these settings are standard, low, and high. The advantage of multiple threshold settings is that by mixing them during ASIC design, optimum power and performance can be achieved. It should be noted that deep submicron ASIC design requires the ability to analyze circuit timing for various voltage, temperature, and process conditions. In both the linear and nonlinear models, characterization would need to be performed for each condition.

To minimize the number of characterizations, the polynomial delay model or current source delay model should be chosen, because the coefficients for the polynomial delay model and the current parameter for the CSM delay model are common for all conditions. Once the coefficients have been calculated, analysis for temperature, or any other condition in an ASIC design, can be performed by inputting conditions as variables to the equations.

During standard cell library characterization, a combination of all the above conditions is used. However, the minimum requirement of an ASIC timing sign-off is to use the worst and the best of all conditions. Chapter One 34 1. In the standard cell section, we outlined the basic cell structure and briefly discussed the concept of Phase Shift Mask process, or PSM, and its impact on standard cell physical design for deep submicron technology. In the transistor sizing section, we reviewed the basic equations involved in standard cell circuit design, and discussed the importance of properly selecting the transistor sizes and their effect on timing performance.

Figure Library Development Steps Libraries 35 In the library characterization section, we gave an overview of the basic concepts of standard cell propagation and transition delay. In addition, we outlined and explained, in the simplest form, some of the more widely used methods for the characterization of standard cells.

We should mention that, although it seems to be a very straightforward task, developing high-quality libraries requires a great deal of expertise and knowledge in the area of circuit design, process, and modeling. References [1] Neil H. Levinsson and William H. Publishing Company, A well thought-out floorplan leads to an ASIC design with higher performance and optimum area.

Before one proceeds with physical floorplanning one needs to make sure that the data used during the course of physical design activity is prepared properly. Proper data preparation is essential to all ASIC physical designs in order to implement a correct-by-construction design. Entire physical design phases may be viewed as transformations of the representation in various steps.

In each step, a new representation of an ASIC is created and analyzed. These physical design steps are iteratively improved to meet system requirements. For example, the placement or routing steps are iteratively improved to meet the design timing specifications. Another challenge commonly faced by physical designers is the occurrence of physical design rule violations during ASIC design verification. If such violations are detected, the physical design steps need to be repeated to Chapter Two 38 correct the errors.

An ASIC Design Implementation Perspective

Sometimes these error corrections have a direct impact on the ASIC timing and may require a re-time of the design to meet timing specifications. Most of the time, the corrections are very time-consuming. Therefore, one of the objectives of physical design is to eliminate or reduce the number of iterations during each step of the design. One of the important keys in reducing the number of iterations is the use of high quality and wellprepared data. The types of data that are required to start a physical design are: x x x x Related technology and library files Circuit description of the design in the form of netlist representation Timing requirements or design constraints Floorplan 2.

Technology files contain information or commands that are used to configure structures, parameters such as physical design rules and parasitic extractions , and limits of an ASIC design targeted to specific process technology. These commands are used at different stages of ASIC design implementation by physical design tools. One of the objectives is to make sure that all parameters in the technology files are set correctly. Once the initial technology file is created, several trial runs need to be performed and results, such as standard cell placement, routing quality, and accuracy of parasitic extraction, should be carefully analyzed.

Based upon the final inspection, technology files may require further refinement for optimal performance. Technology rule basics are as follows: x Manufacturing grid Floorplanning x x x x x x x x x 39 Routing grid Standard cell placement tile Routing layer definition Placement and routing blockage layer definition Via definition Conducting layer density rule Metal layer slotting rule Routing layer physical profile Antenna definition Manufacturing grid is determined by the smallest geometry that a semiconductor foundry can process.

All drawn geometries during physical design must snap to this manufacturing grid. Routing grids or tracks are used by physical synthesis and place-and-route tools during detail routing. The routing tracks can be grid-based, gridlessbased, or subgrid-based. Standard cell placement tile is used during the placement phase. The placement tile is defined by one vertical routing track and the standard cell height. Routing layer definition is used to define the layers that are used to route the design.

These definitions include wire width, routing pitch, and preferred routing direction such as vertical, horizontal, or diagonal. Via definition defines the layer, size, and type for connection between overlapping geometries of conductor for different conductive layers. This cut layer, or via, can be a single via, stacked via, or array of via.

Conducting layer density rule defines the percentage of area of the chip that is required for processes that are using Chemical Mechanical Polishing CMP for each physical layer in the design. The chemical mechanical polishing process requires limited variation in feature density on conducting layers. This dictates that the density of layout Chapter Two 40 geometries in a given region must be within a certain range. With new silicon processes i. Configuration of metal layers slotting rule defines the minimum layer width that may need to have slotting features i.

This rule varies between foundries and is used to limit mechanical stress for a given conducting layer. Physical profile for each layer is used to define and include conductor thickness, height, and interlayer dielectric thickness. Definition of the electrical interconnect profile includes resistance and dielectric constants. Antenna definition for each layer configures the physical design tools for automatic antenna repair.

Antenna phenomena occur during the metallization process when some wires connected to the polysilicon gates of transistors are left unconnected until the upper conducting layers are deposited. A long wire connected to the gate of MOSFT can act as a capacitor or antenna that collects charges during the plasma-etching step.

If this energy build-up on the floating transistor gate is suddenly discharged, the transistor could suffer permanent damage due to gate oxide breakdown. Discussion of how to fix antenna phenomena is presented in Chapter 4. Once the design was captured, the circuit description was imported from capturing tools in some sort of format for physical design. During this time, the rapid emergence of Computer Aided Engineering CAE along with Computer Aided Design CAD technology led to the development of a broad range of interchangeable data formats and hardware description languages.

Unfortunately, most of these circuit descriptions were limited to specific companies and data types. ASIC and physical designers who wished to use a combination of different CAD tools were forced to convert among various Floorplanning 41 formats in order to complete the design. This cumbersome and timeconsuming translation process drove the need for a standard electronic design interchange format.

EDIF is very rich in format and is capable of representing connectivity information, schematic drawings, technology and design rules, and Multi Chip Module MCM descriptions, as well as allowing transfer of documentation associated with physical layouts. This language, however, has been a phenomenal success because it has the utility and ability to meet circuit and system design requirements.

VHDL is independent of design tools and is a powerful language for the modeling of hardware timing. With the introduction of the first logic synthesis tools, the Verilog model that represented the functionality of the circuit designs could be synthesized. This was a major event, as the top-down design methodology could now be used effectively.

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The design could be modeled down at the Register Transfer Level RTL and could then be translated into the gate using synthesis tools. With this event, the use of Verilog modeling increased dramatically. Use of Verilog simulation for sign-off certification by ASIC designers was the next major trend to emerge. However, Verilog remained a closed language and the pressures of standardization eventually caused the industry to shift to VHDL. With standardization, Verilog simulators are now available for most computers, with a variety of performance characteristics and features.

It has truly become the standard hardware description language. Verilog gate-level netlists are widely used owing to their ease of understanding and clear syntax. Although the behavioral Verilog language has a vast number of keywords, there are only a few that may be used in structural Verilog to represent the entire circuit function and connectivity.

A structural Verilog netlist consists of keywords, names, literal comments, and punctuation marks. A Verilog structural netlist is case-sensitive, and all its keywords, such as module, endmodule, input, output, inout, wire, and assign are lowercase. The most basic element in Verilog is a module definition with corresponding input and output ports [1]. It represents a logical entity that is usually implemented in a piece of hardware. A module can be a simple gate or a complex network of gates. The ports in modules can be a single-bit or multiple bits wide, and each port can be defined as an input, output, or inout i.

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The nets that connect the elements inside a module are described by wire statements. For improved readability, spaces, tabs, and new lines can be used. A module in the Verilog language starts with the keyword module followed by the module name, then the list of inputs and outputs. It ends with the keyword endmodule.

Application-specific integrated circuit

Each module name must be unique. Figure represents a logical entity implemented using the Verilog circuit modeling style. The gate level representation or schematic of a structural Verilog netlist, as shown in Figure , is illustrated in Figure These cell types are built into a standard cell library and have predefined functions.


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This implies having a wire which has two distinct names attached at each end. When dealing with the assign keyword, special care must be taken during the physical ASIC verification to avoid misleading results. One of the most frequently used techniques is to replace the assign keyword with a buffer. Floorplanning 45 After processing the imported netlist, the next step is to apply design constraints as explained in the next section.

Each tool attempts to meet two general design constraints: x Timing constraints x Design rule constraints Timing constraints are user-specified and are related to speed, area, and the power consumption of the ASIC design. Timing constraints utilized by physical design tools are performance related. The most basic timing constraints are as follows: x x x x x x System clock definition and clock delays Multiple cycle paths Input and output delays Minimum and maximum path delays Input transition and output load capacitance False paths System clocks, and their delays, are extremely important constraints in ASIC designs.

System clocks are typically supplied externally, but can be generated inside an ASIC. All delays, especially in a synchronous ASIC design, are dependent upon the system clocks. Most logic synthesis tools consider the clock network delays to be an ideal i. This directs the physical design tools to avoid optimization of data paths that have non-single clock behavior. Input and output delays are used to constrain the boundary of external paths in an ASIC design. These constraints specify point-to-point delays from external inputs to the first registers and from registers to the outputs of an ASIC design.

Minimum and maximum path delays provide greater flexibility for physical synthesis tools that have a point-to-point optimization capability. This means that one can specify timing constraints from one specific point e. Input transition and output capacitance loads are used to constrain the input slew rate and output capacitance of an ASIC device input and output pins. These constraints have a direct effect on the final ASIC design timing.

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The values of these constraints are set to zero during physical design and place-and-route activity to ensure that the actual ASIC design timing is calculated independent of external conditions and to make sure register-toregister timing is met. Once that is achieved, these external conditions can be applied to the design for input and output timing optimization.

False paths are used to specify point-to-point non-critical timing either internal or external to an ASIC design. Design rule constraints are imposed upon ASIC designs by requirements specified in a given standard cell library or within physical design tools. Design rule constraints have precedence over timing constraints because they have to be met in order to realize a functional ASIC design. There are four types of major design rule constraints: x Maximum number of fan-outs x Maximum transitions x Maximum capacitance Floorplanning 47 x Maximum wire length Maximum number of fan-outs specify the number of destinations that one cell can connect to for each standard cell in the library.

This constraint can also be applied at the ASIC design level during the physical synthesis to control the number of connections one cell can make. Maximum transition constraint is the maximum allowable input transitions for each individual cell in the standard cell library.

Apart from each element in the standard cell library, this constraint can be applied to a specific net or to an entire ASIC design. Maximum capacitance constraint behaves similarly to maximum transition constraint, but the cost is based on the total capacitance that a particular standard cell can drive any interconnection in the ASIC design. It should be noted that this constraint is fully independent of maximum transition, and therefore, it can be used in conjunction with maximum transition.

Maximum wire length constraint is useful for controlling the length of wire to reduce the possibility of two parallel long wires of the same type. Parallel long wires of the same type may have a negative impact on the noise injection and may cause crosstalk. These design rule constraints are mainly achieved by properly inserting buffers at various stages of physical design. Thus, it is imperative to control the buffering in an ASIC design during place-and-route to minimize area impact. There are two style alternatives for design implementation of an ASIC—flat or hierarchical.

The flat implementation style provides better area usage and requires effort during physical design and timing closure compared to the hierarchical style. The area advantage is mainly due to there being no need to reserve extra space around each subdesign partition for power, ground, and resources for the routing.

Timing analysis efficiencies arise from the fact that the entire design can be analyzed at once rather than analyzing each subcircuit separately and then analyzing the assembled design later. The disadvantage of this method is that it requires a large memory space for data and run time increases rapidly with design size. In addition, it is used when subcircuits are designed individually. However, hierarchical design implementation may degrade the performance of the final ASIC.

This performance degradation is mainly because the components forming the critical path may reside in different partitions within the design thereby extending the length of the critical path. Therefore, when using a hierarchical design implementation style one needs to assign the critical components to the same partition or generate proper timing constraints in order to keep the critical timing components close to each other and thus minimize the length of the critical path within the ASIC.

In the hierarchical design implementation style, an ASIC design can be partitioned logically or physically. Logical partitioning takes place in the early stages of ASIC design i. RTL coding. The design is partitioned according to its logical functions, as well as physical constraints, such as interconnectivity to other partitions or subcircuits within the design. In logical partitioning, each partition is placeand- routed separately and is placed as a macro, or block, at the ASIC top level.

Physical partitioning is performed during the physical design activity. Once the entire ASIC design is imported into physical design tools, partitions can be created which combine several subcircuits, or a large circuit can be partitioned into several subcircuits. Most often, these partitions are formed Floorplanning 49 by recursively partitioning a rectangular area containing the design using vertical or horizontal cut lines. Physical partitioning is used for minimizing delay subject to the constraints applied to the cluster or managing circuit complexity and satisfying timing and other design requirements in a small number of subcircuits.

Initially, these partitions have undefined dimensions and fixed area i. In order to place these partitions, or blocks, at the chip level, their dimensions as well as their port placement must be defined. One method that is suggested to estimate the perimeter of a macro instance is to use the number of terminals or ports allowed for each block and their associated spacing between each terminal [2].

The relationship between the perimeter of each partition and the number of associated terminals is given by P NS , 2. The perimeter estimate given by Equation 2. However, in order to fit each macro instance at the chip top level in an effective manner, the automatic floorplan algorithm needs to have a range of legal shapes that is derived from aspect ratio bounds for each partition in the design.

The aspect ratio bounds that are generated by the hierarchical floorplan algorithm must have the flexibility to ensure that each macro instance shape can be reshaped for optimum placement. Because one requirement for an ASIC design is to fit into the smallest available die size, during the partitioning process for each partition several layout alternatives are considered by modification of the dimensions and terminal placements along the boundary of each partition in the design such that the amount of unused and routing area between each partition is minimized.

Once this data is imported, the physical design tool performs binding operations on the entire netlist for flat design implementation or for each sub-netlist for hierarchical design implementation. During the binding, or linking, process, the incoming netlist is flattened and all entities are analyzed to determine their available models. A variety of checks is performed automatically to determine whether the physical synthesis or place-and-route internal data structure is ready to proceed with the rest of the design implementation flow.

New Book Physical Design Essentials: An ASIC Design Implementation Perspective

Often the checks that detect problems with the physical database are related to the netlist, such as unconnected ports, mismatched ports, standard cell errors, or errors in the library and technology files. Because of these checks, a log file that contains all errors and warnings will be generated. It is important to review the log file and make sure that all reported errors and warnings are resolved before proceeding to the next phase.

Regardless of the physical design implementation style, after physical database creation using the imported netlist and corresponding library and technology files, the first step is to determine ASIC device and core width and height. Figure shows an initial ASIC design floorplan. The height of a row is equal to the height of the standard cells in the library.

If there are any multiple-height standard cells in the library, they will occupy multiple rows. Most of the time, standard rows are created by abutment. The standard rows are oriented in alternating degree rotation or are flipped along the X-axis so that the standard cells can share power and ground busses. If the ASIC core has routing congestion owing to the limited number of routing layers, one solution is to create routing channels between rows.

These all can be separated individually or as pairs. These pads are power, ground, and signal. It is critical to functional operation of an ASIC design to insure that the pads have adequate power and ground connections and are placed properly in order to eliminate electromigration and current-switching noise related problems. Electromigration currents exceeding recommended guidelines can result in premature ASIC device failure. Exceeding electromigration current density limits can create voids or hillocks, resulting in increased metal resistance, or shorts between wires, and can impair ASIC performance.

Figure Electromigration Damage Using Equation 2. The required number of power pads is equal to the required number of ground pads and is given by N gnd I total , I max 2. An inadequate number of power and ground pads will lead to system data errors due to these switching noise transients. This noise problem can be resolved by proper pad placement, package pin selection, ASIC output pad type and drive current, and input pad type. The inductance in the power and ground pins cause voltage fluctuations in the ASIC internal power and ground level relative to the external system.

Factors such as process, ambient Chapter Two 54 temperature, voltage, location of output pads, and number of simultaneous switching output pads determine the magnitude of inductive switching noise. To control inductive switching noise, enough power and ground pads must be assigned and placed correctly. This way the noise magnitude will be limited.

This noise reduction will prevent inputs of ASIC design from interpreting the noise as valid logic level. Successful reduction of inductive switching noise can be accomplished by the following: x Reduce the number of outputs that switch simultaneously by dividing them into groups with each group having a number of delay buffers inserted into their data paths x Use the lowest rated sink current or low-noise output pads as long as speed is not an issue x Place the simultaneously switching output or bidirectional pads together and distribute power and ground pads among them according to their relative noise rating x Assign static and low frequency input pads to higher inductance package pins x Reduce the effective power and ground pin inductance by assigning as many power and ground pads as possible 2.

For core logic, there is a core ring enclosing the core with one or more sets of power and ground rings. A horizontal metal layer is used to define the top and bottom sides, or any other horizontal segment, while the vertical metal layer is utilized for left, right, and any other vertical segment. These vertical and horizontal segments are connected through an appropriate via cut. The next consideration is to construct the standard cell power and ground that is Floorplanning 55 internal to the core logic.

These internal core power and ground busses consist of one or two sets of wires or strips that repeat at regular intervals across the core logic, or specified region, within the design. Each of these power and ground strips run vertically, horizontally, or in both directions. Figure illustrates these types of power and ground connections. Figure Ring and Core Power and Ground If these strips run both vertically and horizontally at regular intervals, then the style is known as power mesh.

The total number of strips and interval distance is solely dependent on the ASIC core power consumption. As the ASIC core power consumption dynamic and static increases, the distance of power and ground strip intervals increases.


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A macro ring encloses one or more macros, completely or partially, with one or more sets of power and ground rings. Another important consideration is that when both analog and digital blocks are present in an ASIC design, there is a need for special care to insure that there is no noise injection from digital blocks or core into the sensitive circuits of analog blocks through power and ground supply connections.

Much of this interference can be minimized by carefully planning the power and ground connections for both digital core and analog blocks. There are several methods to improve the noise immunity and reduce interference. In order to make sure that analog circuits are completely decoupled from digital circuits, one needs to separate the substrate from the ground in the standard cells e. This is not mandatory but depends on how sensitive the analog circuit is with respect to noise injection from the digital core area. This increase in power and ground width could be problematic from manufacturing point of view.

The main problem with wide metal i. The metal becomes thin in the middle and thick on the edges causing yield and current density problems. To solve this metal density problem, one can either use multiple power and ground busses or use metal slotting. These maximum specified widths for different metal layers are determined by semiconductor manufacturers as a slot-width and need to be included in the physical design tool technology file.

Chapter Two 58 2. Macros may be memories, analog blocks, or in the case of hierarchical style, an individually placed and routed subcircuit. Proper placement of these macros has a great impact on the quality of the final ASIC design. Macro placement can be manual or automatic. Manual macro placement is more efficient when there are few macros to be placed and their relationship with the rest of the ASIC design is known. During the macro placement step, one needs to make sure that there is enough area between blocks for interconnections. This process commonly known as channel allocation or channel definition can be manual or can be accomplished by floorplan tools.

The slicing tree is used by the floorplan algorithm for slicing floorplan during macro placement and to define routing channels between the blocks. Wire length optimization is the most prevalent approach in automatic macro placement. With increases in the number of embedded blocks such as memories, placing macros of varying sizes and shapes without a good optimization algorithm can result in fragmentation of placement and routing space that can prevent a physical design from being able to complete the final route.

One of the basic algorithms used for automatic macro placement considers that macros are connected to each other by nets and are supposed to exert attractive forces on each other by means of wire length proportional to the distance between these macros. Automatic macro placement is an iterative process. During the macro placement process, macros are free to move until the equilibrium or optimum wire length is achieved. It is interesting to note that in this algorithm, if there is no Floorplanning 59 relationship between the macros, they tend to repel each other and their placement result may not be optimum.

To improve the placement quality of macros that are not related to each other, one may consider simultaneous standard cell and macro placement provided the physical design tool can deal with both macro and standard cell placement at once. In terms of algorithms, while commercial physical design tools have considerably improved in the past few years, automatic macro placement is still in the early stages of development compared to standard cell placement. The implementation challenge associated with macro placement is conceptually a time and space problem that needs to be solved simultaneously.

A well-developed macro placement algorithm must be able to handle widely differing shapes and sizes, macro orientation, congestion, and timing-driven placement. When it is not an easy task to measure the macro placement quality of an ASIC design containing a large number of blocks, there are some basic physical measurements that one can adopt. Given a placement solution, the physical measurements could be wire length, data flow direction e. The total wire length for a given placement is a good indicator when comparing different placements of the same physical design.

To avoid area segmentation, macros should be positioned such that the standard cell area is continuous. An area with close to aspect ratio is recommended as it allows standard cell placers to utilize the area more efficiently and thereby reduce total wire length. Chapter Two 60 The segmented floorplan leads to an excess of wire length interconnections from the standard cells located at the bottom of the die to those at the top of the die.

Thus, it is necessary that the macros be kept along the ASIC core area in order to avoid a floorplan segmentation problem. Figure shows a problematic segmented floorplan that may lead to long interconnections between the bottom and top of the die. Figure Segmented Floorplan Another aspect of increased wire length is related to macro placement with respect to their orientation and pin placements.

Depending on the macro orientation and their actual pin location, the length of the nets connecting to the macros can be different, and can have significant impact on the routing optimization process. With respect to wire length reduction, macros should be oriented such that their ports are facing the standard cells, or core area, and their orientation should match the available routing layers. Figure shows a floorplan with macro ports facing the standard cell region, thereby minimizing localized increase in wire length.

The macro placement, and thereby the quality measure, can be determined by the analysis of routing congestion produced by a global router. Most global routers are capable of producing both graphical and text statistical reports. The graphical report, also referred to as the congestion map, provides a visual aid to see where routing congestion exists e. The statistical report is a good indication of how much a physical design is congested. Standard cell trap pockets are long, thin channels between macros. If many cells are placed in these channels, routing congestion can result.

Therefore, these channels need to be kept free for most standard cells and should be available for repeater or buffer insertion if this type of insertion is supported by the physical design tool. Figure shows a floorplan with a standard cell trap pocket.

Figure Floorplan with Standard Cells Trap Pocket After macro placement and before performing global routing, most physical designs require keep-out or buffer-only regions to be defined by drawing a Floorplanning 63 blockage layer over an area containing macros to prevent the placer from moving any standard cells into those regions. Naturally, the wires that are used in keep-out regions have a tendency to be long. By allowing buffer insertion in those areas by using a buffer-only region or blockage , the placer will taper these long nets and thus avoid the long transition times associated with them.

These blockage layers are created over pre-placed macros such that their power and ground rings are covered. When a macro is blocked on many routing layers, wires have a tendency to detour around corners and connect to nearby standard cells thereby creating routing congestion at the corner of the macros. To reserve more resources for the router, one can draw a blockage layer at these corners.

These blockage regions can be simple or gradual as illustrated in Figure Figure Macro Corner Standard Cells Blockage After refinement of floorplan and macro placement, standard cells are placed and connectivity analysis is performed. Connectivity analysis is also used to identify macros that have substantial direct connectivity and to refine their locations accordingly. This analysis is conducted by using what is known as fly lines. When fly lines are activated through physical design or place-and-route tools, Graphic User Interface GUI displays the lines that mark the connections between currently selected instances e.

Using fly lines, one can analyze and identify situations where moving or rotating macros will yield shorter wire lengths that improve the overall ASIC routability during the floorplanning stage of the physical design cycle. The idea of the implementation of clock distribution networks is to provide clock to all clocked elements in the design in a symmetrically-structured manner. Although most ASIC designs use clock tree synthesis, clock tree synthesis may not be sufficient for very high-performance and synchronized designs.

In this case, one needs to implement the distributed clock networks manually in order to minimize the skew between communicating elements due to their line resistance and capacitance. It is important to note that this type of clock grid does not rely on the matching of components such as clock buffers. However, it can present a systematic clock skew.

In order to minimize such clock skew, a clock tree that balances the rise and fall time at each clock buffer node should be utilized during clock planning. This minimizes the hot-electron effect. The problem of hot-electron occurs Floorplanning 65 when an electron gains enough energy to escape from a channel into a gate oxide.

The presence of hot-electron effect in the gate oxide area causes the threshold voltage of the device to change and thus alters the delay of the clock buffers. This in turn leads to an additional skew. Hence, balancing the rise and fall times of all clock buffers means that hot-electron effect influences the clock buffers at the same rate, minimizing unpredictable skew. Figure Clock Distribution Network It is essential to realize that clock grid networks consume a great deal of power due to being active all the time and it may not be possible to make such networks uniform owing to floorplanning constraints e.

Another aspect of clock planning is that it is well suited to hierarchical physical design. This type of clock distribution is manually crafted at the chip level, providing clock to each sub-block that is place-and-routed individually. Chapter Two 66 To minimize the clock skew among all leaf nodes, the clock delay for each sub-block must be determined and the design of the clock planned accordingly. Figure illustrates typical hierarchical clock planning. Figure Hierarchical Clock Planning 2. In the area of data preparation, we have provided a general idea of the technology files that are required by physical design tools, and have provided an example of a Verilog structural netlist with the most common description of its syntax and keywords.

Floorplanning 67 In the design constraint section, we have discussed several important timing and design constraints and their impact on the quality of the ASIC physical design. Figure Basic Floorplanning Steps In the design implementation section, we have outlined the fundamentals of different floorplanning styles, mainly flat and hierarchical, and their advantages, and we have explained basic floorplanning techniques.

In addition, we have outlined the importance of automatic partitioning of a design, and port optimization and minimization for ASIC design. In the input-output section, we have explained placement and given basic guidelines with respect to coupling capacitance and inductive switching. In the power and ground section, we have shown several styles of creating power and ground connections.

Again, depending upon the floorplanning style, the power and ground connections need to be designed to meet the ASIC power requirements and can vary from design to design. In the macro placement section, we have illustrated various macro placements based on industry practices. In addition, we should note that regardless of what style of macro placement is used during floorplanning, a well thought-out floorplan and macro placement leads to a higher quality of the final ASIC design with respect to performance and area.

Finally, in the clock planning section we have briefly discussed the manual clock planning topology and its importance for high-speed design applications. Figure exhibits the basic steps that are involved during the physical design floorplanning phase. Standard cell libraries are an important part of many of today's integrated circuit IC designs. The design of all digital ASICs Application Specific Integrated Circuit essentially involves the use of an ASIC standard cell library comprising logic functional primitives such as basic gate functions, complex combinational functions, sequential elements, arithmetic elements and 1I0s.

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